1. Field of the Invention
The present invention relates to a method for amending layout patterns. More particularly, the present invention relates to a method for selectively amending layout patterns.
2. Description of the Prior Art
Critical technologies such as the photolithography and etching technologies are frequently used in semiconductor manufacturing processes. The photolithography technology usually involves transferring a complicated integrated circuit pattern to a semiconductor wafer surface for steps such as etching and implantation. These patterns must be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps.
In the photolithographic step, deviations often occur and jeopardize the performance of the semiconductor device when the patterns on the reticles are transferred onto the wafer surface. Such deviations are usually related with the characters of the patterns to be transferred, the topology of the wafer, the source of the light and various process parameters.
There are many known verification methods, correction methods and compensation methods for the deviations caused by the optical proximity effect, process rules (PRC) and lithography rules (LRC) to improve the image quality after transfer. Some of the known methods are called optical proximity correction (OPC), process rule check (PRC) and lithography rule check (LRC). The commercially available OPC software may test problems such as pitch, bridge, and critical dimension uniformity in the layout patterns. Such software may correct the standard layout patterns on the reticles using the theoretical image, so as to obtain correctly exposed image patterns on the wafers. Such methods not only test problems in the layout patterns but also correct the layout patterns on the reticles using the theoretical image. If the corrected image patterns are useable, they are output for the fabrication of reticles to obtain the correct image patterns on the wafer.
Generally speaking, there are well-established stand operational procedures available for the reference of the above-mentioned verification, correction and compensation methods. For example, the conventional procedure using optical proximity correction to verify the layout patterns on a reticle may be first inputting a layout pattern. Then the Boolean pre-treatment of OPC is performed on the layout pattern to obtain a preliminary layout pattern. Afterwards the OPC is performed to correct any particular pattern. Later, the process rule check (PRC) and the lithography rule check (LRC) are separately performed. Then the error screening and check is performed. If the obtained patterns are correct and usable, the patterns are output. If incorrect, the pattern correction is performed again and the patterns are output if no error is found.
Accordingly, it is an essential operational procedure in the manufacturing process of semiconductors to use the optical proximity correction model to correct the layout patterns to obtain useable layout patterns and to make the transfer of such layout patterns more precise.